In the field of integrated circuit technology, the invention of the circuit concept known as MTL (Merged Transistor Logic) or I.sup.2 L (Integrated Injection Logic) has to a large extent provided the advantages of traditional bipolar techniques (high switching speed) combined with the advantages of Field Effect Transistor techniques (high integration density, low power dissipation). Of the number of articles published on I.sup.2 L in the trade literature reference is made to the following: (1) "Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept" by Horst H. Berger and Siegfried K. Wiedmann, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972 pages 340 through 346, and (2) "Injection Integrated Logic: A New Approach to LSI", by Kees Hart and Arie Slob, Vol. SC-7, No. 5, October 1972, pages 346 through 351.
Subsequently, developments based on the above (injection) concept have become known under various designations. In these developments, the carrier current emanating from a (primary) injector on its way to a collecting area may be switched in a condition-dependent manner via various control regions arranged in the path. In other words, the so-called secondary injection in PNP chains is utilized for the forming of logic combinations.
Reference is made to the following publications:
"Current Hogging Injection Logic: New Functionally Integrated Circuits" by Rudiger Muller (ISSCC 75/Friday, Feb. 14, 1975/Brandywine Ballroom/9:00-12:00) Digest of Technical Papers, 1975 IEEE International Solid-State Circuits Conference, pages 174, 175;
"Current Hogging Injection Logic--A New Logic with High Functional Density" by Rudiger Muller, IEEE Journal of Solid-State Circuits, Vol. SC-10, No. 5, October 1975, pages 348 through 352; and
"Current Hogging Logic (CHL)--A New Bipolar Logic for LSI" by Heinz Lehning, IEEE Journal of Solid State Circuits, October 1974, pages 228 through 233.
Reference is also made to U.S. Pat. No. 4,035,664 entitled "Current Hogging Injection Logic" granted July 12, 1977 to Horst H. Berger and Siegfried K. Wiedmann.
In the fabrication of known designs of logic circuit structures, based on the injection principle, where logic functions of input variables are to be executed, at least three dimension-determining masks (including the contact holes without metallization pattern) are required. If processing starts, for example, with an N-doped semiconductor material a first mask is required for generating the P-doped conductive areas of the PNP structures. By means of a second mask, the N-doped conductive areas within certain P-areas for the NPN structures are defined. Finally, a third mask is required for providing the contact holes to the respectively doped areas. The subsequent known manufacturing process steps are not of interest for the purposes of this explanation. Hence, it is deemed unnecessary to recite same.
The invention provides improvements in Current Hogging Injection Logic circuits and an improved method of fabricating same. The method of fabrication provides for the straight forward relatively easy and non-critical production of said improved circuits, with fewer masks. Further, semiconductor logic circuit structures, in accordance with the invention provide increased integration density and improved power-delay product per logic function. Thus, from an economic point of view, a major advantage of the invention is a further decrease of the manufacturing costs of such circuits in that the function density in a predetermined packing density is increased, or in that a maximum of circuit functions are housed on one entire semiconductor substrate (chip).
Briefly, the invention, in its more generalized form for the direct realization of logic combinations of input variables provides that, in a semiconductor arrangement with at least two doping areas placed one within the other, of which at least the outer one is to be electrically accessible, a surface contact is provided not in that area directly but in an adjacent area of the same conductivity. The functional coupling to the outer one of the at least two doping areas placed one within the other takes place via injection coupling. For an NPN transistor structure this means, by way of example, that the base contact area is separated from the intrinsic base and arranged before it. The connection is made through hole injection. Due to the contact area separation a much simpler manufacturing process may be used for circuits of this type. This is because the doped areas and if necessary, even the contact openings are jointly definable as minimum surfaces through one single mask, with only a relatively uncritical rough mask (so-called blockout mask) being added thereto.
In the prior art a semiconductor arrangement is known where between an injector area and an NPN output transistor, which has no external base contact, there is another area having an external contact and being of the same conductivity type as the transistor base area. Reference is made to "Bipolar LSI Takes A New Direction with Integrated Injection Logic" by C. M. Hart, A. Slob and H. E. J. Wulms, Electronics of Oct. 3, 1974, pages 111 through 118, (page 114). However, the semiconductor arrangement shown there explicitly serves for the voltage level adaptation required at the interface of different circuit concepts, namely I.sup.2 L/TTL. There is no teaching or suggestion whatever regarding the execution of logic combinations. The publication is devoid of a teaching or suggestion of the advantageous and efficient manufacturing and masking steps of the process of the present invention. In particular, the output of the level adapter circuit is not the original logic output where the logic result is generated for the first time. Indeed, the respective logic operation is executed in the preceding conventional I.sup.2 L circuit portion and is available at the input of the level adapter circuit.
As to the forming of two doped areas through a single mask opening, reference is made to GE-OS No. 1,789,055. More specifically, GE-OS No. 1,789,055 discloses twice diffusing through the same oxide window to provide PN capacitors.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments as illustrated in the accompanying drawings.